Semiconductor devices which employ SiGe are being vigorously studied to attain goals such as reduction of power consumption and enhancement of operation speed in semiconductor devices. By using an SiGe layer as a channel, hole mobility can be improved about twofold over that in a conventional silicon layer. Studies of strained Si technology are also in progress. By using a strained Si layer as a channel layer, an about 2.2 times improvement in electron mobility, and an about 1.4 times improvement in hole mobility, can be realized over that of a conventional silicon layer. Such a strained Si layer can be obtained by growing an Si layer on a lattice-relaxed SiGe layer. Since SiGe crystal has a slightly larger lattice mismatch than that of Si (the lattice constant of an SiGe layer having a 30% Ge composition is about 1% greater than the lattice constant of a silicon layer), tensile strain will occur in the Si which is grown on SiGe.
The inventors have studied development of a semiconductor device in which a semiconductor layer including an SiGe layer is selectively epitaxially-grown in specific regions of an Si substrate, such that usual Si MOS transistors (Si devices) and SiGe MOS transistors (SiGe devices) coexist on a single Si substrate.
In order to allow such MOS transistors whose channel regions differ in semiconductor composition to coexist on a single Si substrate, it is necessary to grow an SiGe layer in selected regions of the Si substrate, uniformly and with a good reproducibility.
With reference to FIGS. 6(a) and (b), a basic method for growing an SiGe layer on a selected region will be described. FIG. 6(a) is a plan view showing a portion of a principal face of an Si substrate 1, where device active regions 50 and 60 and an isolation region 70 are illustrated. FIG. 6(b) is a cross-sectional view taken at line B-B in FIG. 6(a).
As can be seen from FIGS. 6(a) and (b), on the principal face of the Si substrate 1, an SiGe-containing layer is epitaxially grown on the surface of the device active region 50, whereas nothing is grown on the surface of the device active region 60. Moreover, the device active regions 50 and 60 are within the surrounding isolation region 70. In the device active region 50, an MOS transistor (SiGe device) which utilizes the SiGe-containing layer as an active region is formed through subsequent production steps (not shown). In the device active region 60, an MOS transistor (Si device) which utilizes the surface region of the Si substrate 1 as an active region is formed.
In the isolation region 70, as shown in FIG. 6(b), a recess or trench whose interior is filled with an insulator 30 is formed. The level of the substrate principal face (Si surface) in the isolation region 70 is lower than the level of the substrate principal face (Si surface) in the device active regions 50 and 60. Such a device isolation structure, comprising the insulator 30 which fills a device isolation trench that is formed in the Si substrate 1, is called STI (Shallow Trench Isolation). The device active regions 50 and 60 are electrically separated from each other by this STI.
Only two device active regions 50 and 60 are illustrated in FIGS. 6(a) and (b) for simplicity. A multitude of device active regions 50 and 60 are to be formed on an actual Si substrate.
Before the SiGe-containing layer is epitaxially grown on the device active region 50, a selective-growth mask (not shown) which completely covers the surface of the device active region 60 is formed. The selective-growth mask has an aperture formed therein, such that the device active region 50 is left exposed through this aperture immediately prior to epitaxial growth. Under selective epitaxial conditions, the SiGe-containing layer will grow its crystal on the Si surface, while not growing on the selective-growth mask. Therefore, the SiGe-containing layer is selectively grown on the device active region 50, as shown in FIG. 6(b).
Note that, in order to form STI, an insulating film such as SiO2 is deposited so as to fill a device isolation trench which is formed on the surface of the Si substrate 1, and thereafter a treatment of planarizing the upper face of the insulating film by CMP (Chemical Mechanical Polishing) is performed. When performing such CMP, there may emerge differences in polishing amount within the isolation region 70, between portions having broader areas and portions having narrower areas, thus hindering a uniform planarization treatment. Such a phenomenon is called “dishing”, where the polishing amount varies depending on the pattern size or area ratio. In order to solve the dishing problem, as shown in FIGS. 7(a) and (b), it is practiced to form a plurality of dummy regions 80 within the isolation region 70 (Patent Document 1, for example). The dummy regions 80 are formed with the purpose of substantially uniformizing the trench width of the STI across the wafer or within the chip, thus ensuring that polish by CMP will uniformly progress in the wafer. Therefore, although the dummy regions 80 are positioned in portions of the region where a recess (as the isolation region 70) is to be formed, no recesses are formed in such portions. As a result, the Si surface of the dummy regions 80 is maintained at the same level as that of the Si surface of the device active regions 50 and 60. However, no devices such as transistors are formed in the dummy regions 80. When polishing by CMP an insulating film for the STI, the upper face of the dummy regions 80 is covered with an SiN layer, as are the upper faces of the device active regions 50 and 60. This SiN layer will be removed after finishing CMP.
Conventionally, the aforementioned selective-growth mask is patterned so as to completely cover the dummy regions 80, and therefore no SiGe-containing layer will epitaxially grow on the dummy regions 80.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 11-16999